1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing the semiconductor devices.
2. Description of the Related Art
Vertical MOSFETs using silicon carbide (SiC) used as a switching device have a stacked structure in which an n-type SiC layer is laminated on a top surface of an n+-type SiC substrate. A gate structure and a source structure are provided at the top surface side of the SiC layer. A drain structure is provided in a bottom surface side of the SiC substrate. During an operation of a vertical MOSFET, a high electric field is applied to the top surface side of the SiC layer. Therefore, a junction gate field-effect transistor (JFET) region is provided so as to have immunity against the high electric field.
The provision of the JFET region leads to an increase in on-state resistance because of large resistance component of the JFET region to result in an increase of loss at the time of switching. In order to reduce the on-state resistance, JP 2011-159797A discloses a method of uniformly increasing a concentration of n-type impurities in a JFET region. JP 2015-056644A also discloses that a p-type region is deposited on an n-type drift region by epitaxial growth, and a p+-type base region is buried in the p-type region by ion implantation, so as to minimize an increase in on-state resistance.
The uniform increase of concentration of the n-type impurities in the JFET region for reducing the on-state resistance, as disclosed in JP 2011-159797A, can decrease a reduction of a breakdown voltage to a certain extent, whereas the reduction of the breakdown voltage is unavoidable because of the increase of the impurity concentration. Further, the structure as disclosed in JP 2015-056644A in which the p-type region is deposited on the n-type drift region, and the p+-type base region is buried in the p-type region, hinders the formation of an n-type region below the p+-type base region, and a difficulty lies in suppressing spreading resistance of the JFET region.